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Freescale Semiconductor /MKM14ZA5 /AFE /CH0_CFR

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Interpret as CH0_CFR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)HW_TRG 0 (0)DEC_CLK_INP_SEL 0 (0)DEC_CLK_EDGE_SEL 0 (0)CC 0 (0)DEC_EN 0 (0)SD_MOD_EN 0 (0)BYP_MODE 0PGA_GAIN_SEL 0 (0)PGA_EN 0 (000)DEC_OSR

HW_TRG=0, SD_MOD_EN=0, PGA_EN=0, DEC_EN=0, DEC_CLK_INP_SEL=0, DEC_OSR=000, BYP_MODE=0, CC=0, DEC_CLK_EDGE_SEL=0

Description

Channel0 Configuration Register

Fields

HW_TRG

Hardware Trigger Select

0 (0): Software trigger select

1 (1): Hardware trigger select
DEC_CLK_INP_SEL

Decimator Clock Input Select

0 (0): On the chip modulator clock will be used

1 (1): External clock will be used.
DEC_CLK_EDGE_SEL

Decimator Clock Edge Select

0 (0): Posedge will be used.

1 (1): Negedge will be used.
CC

Continuous Conversion/Single Conversion Mode Select

0 (0): One conversion following a triggering event

1 (1): Continuous conversions following a triggering event.
DEC_EN

Decimation Filter enable

0 (0): Decimation filter is disabled.

1 (1): Decimation filter is enabled.
SD_MOD_EN

Sigma Delta Modulator enable

0 (0): SD ADC1 is disabled

1 (1): SD ADC1 is enabled
BYP_MODE

AFE Channel bypass mode

0 (0): Normal mode

1 (1): Bypass mode where ADC and PGA of the appropriate channel are disabled.
PGA_GAIN_SEL

PGA Gain Select

1 (001): 1x (default)

2 (010): 2x

3 (011): 4x

4 (100): 8x

5 (101): 16x

6 (110): 32x
PGA_EN

PGA enable

0 (0): PGA disabled

1 (1): PGA enabled
DEC_OSR

Decimator OverSampling Ratio select

0 (000): 64

1 (001): 128

2 (010): 256

3 (011): 512

4 (100): 1024

5 (101): 2048

Links

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Register License

Redistribution and use in source and binary forms, with or without modification,\nare permitted provided that the following conditions are met:\n o Redistributions of source code must retain the above copyright notice, this list\n of conditions and the following disclaimer.\n o Redistributions in binary form must reproduce the above copyright notice, this\n list of conditions and the following disclaimer in the documentation and/or\n other materials provided with the distribution.\n o Neither the name of Freescale Semiconductor, Inc. nor the names of its\n contributors may be used to endorse or promote products derived from this\n software without specific prior written permission.\n THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS “AS IS” AND\n ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\n WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\n DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR\n ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\n (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\n LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\n ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\n (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\n SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data